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Catherine Gebotys

Professor
ELECTRICAL AND COMPUTER ENGINEERING
University of Waterloo
Canada

Biography

Catherine Gebotys received the B.A.Sc. degree in engineering science in 1982 and the M.A.Sc. degree in electrical engineering in 1984, both from University of Toronto, Toronto, Ont., Canada. She received the PhD degree in electrical engineering in 1991 from the University of Waterloo, Waterloo,Ont Canada. She worked at Litton Systems Canada Ltd from Jan 1985 to Dec 1986 in the area of CAD for VLSI and chip design. From Jan 1987 to Aug 1989 she was a research associate in the VLSI group, Dept of Electrical Engineering, University of Waterloo. She is currently a Professor and has been with the Dept of Electrical and Computer Engineering, University of Waterloo since Sept 1991. She has published a number of research papers in the area of side channel analysis, embedded security, applied optimization for high-level hardware and software synthesis. She is the author of 'Security in Embedded Devices', Springer, 2010 (as well as coauthor of 'Optimal VLSI Architectural Synthesis: area, performance and testability', Norwell,MA:Kluwer, 1992). She was Technical Program Co-Chair of CODES+ISSS 2008 and she has served on several technical program committes (CHES, DAC, CODES+ISSS, International Symposium on System Synthesis, DATE). Dr Gebotys is the Deputy Editor-in-Chief of the IEEE Embedded Systems Letters, an Associate Editor for IEEE Transactions on VLSI and an Associate Editor for DAES the Springer Verilag Journal. She is the sole inventor of several patents and she has also received awards including the CITO Champions of Innovation Award. She has collaborated with several companies including DRDC, XtremeEDA, Blackberry, ESA, Kili, Motorola, ViXS, COMDEV, etc. Her research interests include embedded systems security, side channel (power/electromagnetic) analysis of cryptographic algorithms, reconfigurable computing models, global optimization approaches to compilation for DSP processors, low-power systems synthesis, and high-level architectural synthesis.

Research Interest

Security on SoCs, Power/EM analysis (Simple power analysis (SPA), â€‹Differential power analysis (DPA)), security for portable devices Low power Digital Signal Processing (DSP) systems design Architectural synthesis

Publications

  • Gebotys CH, Ho S, Tiu CC. EM analysis of rijndael and ECC on a wireless java-based PDA. InInternational Workshop on Cryptographic Hardware and Embedded Systems 2005 Aug 29 (pp. 250-264). Springer, Berlin, Heidelberg.

  • Aranha DF, Karabina K, Longa P, Gebotys CH, López J. Faster Explicit Formulas for Computing Pairings over Ordinary Curves. InEurocrypt 2011 May 15 (Vol. 6632, pp. 48-68).

  • Gebotys CH, Elmasry MI. Global optimization approach for architectural synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 1993 Sep;12(9):1266-78.

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