Maria K. Michael
Department of Electrical and Computer Engineering
Cyprus University of Technology
Maria K. Michael holds B.Sc. (summa cum laude) and M.Sc. degrees in Computer Science, and a Ph.D. in Engineering Sciences (specialization in Computer Engineering) from Southern Illinois University, USA. Prior to joining the University of Cyprus, she has taught as a Lecturer at the ECE Department at Southern Illinois University, and as an Assistant Professor of Computer Science and Engineering at the University of Notre Dame, USA. She is currently an Associate Professor with the Electrical and Computer Engineering Department at the University of Cyprus. Her research expertise falls in the areas of test and reliability of digital circuits and chip-level architectures, with emphasis on state-of-the-art CAD algorithms for automatic testing, diagnosis and verification, as well as fault tolerance and reliability, applicable to large-scale VLSI circuits and reusable embedded cores integrated into whole chip-level architectures and large-scale on-chip multiprocessors. Recent research interests expand to design and optimization of embedded systems and other chip-level architectures, dynamic self-detecting and self-healing architectures, and dependability/reliability /availability in the hardware backbone of the computing continuum, enabling IoT and cyber-physical systems. Current research focuses on dynamic and intelligent state-of-the-art parallel CAD algorithms for automatic testing and fault simulation, embedded and general-purpose multi-/many-core systems reliability and on-line testing, intelligent methods for design, test and fault tolerance, delay test and emerging fault models, and decision diagrams and their applicability in test/diagnosis CAD problems. Her research has been funded by the University of Cyprus, the University of Notre Dame, USA, the Cyprus Research Promotion Foundation, Intel Corporation, and the European Union RTD Framework Programme. Part of her work was nominated for a Best Paper Award, IEEE International Symposium on Quality Electronic Design, 2005, and the Best Dissertation of the Year Award at SIU-C by the College of Engineering, SIU-C in 2002. She is the co-recipient of a Best Paper Award by the IEEE Microelectronics Systems in Education Conference, July 2009. Between 2009-2013, she co-founded and co-organized the International Workshop on Design for Reliability (DFR), which was held in conjunction with the International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), aiming to stimulate interest in the emerging and challenging issues of reliability-aware design by bringing together researchers from various areas (design, verification, test, architecture, fault-tolerance and reliability) to share ideas and foment future research in holistic approaches for reliable next-generation computing systems. Between 2011-2015 she was a member of the Management Committee of the EU ICT COST Action on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN) and a Vice-Chair of the MEDIAN workgroup on Dependability evaluation and validation/debug methodologies. Maria has served on numerous organizing and technical program committees of various conferences. She was Technical Program Chair for the 28th IEEE Annual International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS'15, MA-USA), General Chair of DFTS'16, and General Chair for the 22nd IEEE European Test Symposium (ETS) hosted in Cyprus. She is a member of the IEEE.
Fault tolerance and reliability of digital systems Test automation and diagnosis of electronic circuits and systems Design for testability Embedded and general-purpose multi-/many-core systems reliability and on-line test Intelligent methods for design, test and fault tolerance Test-based/semi-formal verification and timing analysis - Graph theory and (parallel) algorithms for CAD tools; decision diagrams and SAT
H. Kim, S. B. Boga, A. Vitkovskiy, S. Hadjitheophanous, P. V. Gratz, V. Soteriou and M. K. Michael, “Use it or Lose it: Proactive, Deterministic Longevity in Future Chip Multiprocessors”, ACM Transactions on Design Automation of Electronic Systems, Vol. 20, No. 4, September 2015, pp. 1-26.
M. Maniatakos, M. K. Michael and Y. Makris, “Multiple-Bit Upset Protection in Microprocessor Memory Arrays using Vulnerability-based Parity Optimization and Interleaving”, IEEE Transactions on Very Large Scale Integration, to appear, published online (IEEE Xplore), DOI Bookmark: 10.1109/TVLSI.2014.2365032, November 2014, pp. 1-13.
M. Skitsas, C. Nicopoulos and M. K. Michael, “DaemonGuard: Enabling O/S-Orchestrated Fine-Grained Software-Based Selective-Testing in Multi-/Many-Core Microprocessors”, IEEE Transactions on Computers, to appear, published online (IEEE Xplore),DOI Bookmark: 10.1109/TC.2015.2449840, June 2015, pp. 1-14.