Zdeněk Pohl
Head of Department
Department of Signal Processing
Institute of Information Theory and Automation of the CAS
Czech Republic
Biography
Zdeněk Pohl working as vice-head of department in the Department of Signal Processing in the Institute of Information Theory and Automation. His research interest is Informatics and programmable logic, FPGA implementations.
Research Interest
Informatics and programmable logic; parallel and extremely fast system-identification algorithms; FPGA implementations
Publications
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Kadlec JiÅ™Ã, Pohl ZdenÄ›k, Kohout Lukáš (2017) Full HD Video Processing in HW with three EdkDSP 8xSIMD Accelerators for TE0715-30-1 SoM on TE0701-06 Carrier.
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Kadlec JiÅ™Ã, Pohl ZdenÄ›k, Kohout Lukáš (2016) Asymmetric Multiprocessing with MicroBlaze, EdkDSP Accelerator and Toshiba Sensor Video for Automotive grade Zynq on TE0720-03-1QF SoM on TE0701-05 Carrier.
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Pohl Z, Tichy M, Kadlec J. Implementation of the least-squares lattice with order and forgetting factor estimation for FPGA. EURASIP Journal on Advances in Signal Processing. 2008 Jan 1;2008:150.
