Dr. Ravneet Kaur

Biography

Dr. Ravneet Kaur (Assistant Professor) specializes in analytical analysis, characterization and simulation of short channel effects in sub-100nm MOSFET for high performance. Her research areas focused on the development of efficient 2D algorithms and optimization techniques for advanced sub-100nm MOS structures. Consideration has also been given to exploration of new architectures of Silicon on Insulator and Silicon On Nothing MOSFETs for enhanced performance and their applications in various different fields. She has also worked on modeling and simulations of HEMTs for high performance microwave circuits. She has authored or co-authored more than 66 papers in various international and national journals and conference proceedings. Dr. Kaur has been a reviewer for IEEE TRANSACTIONS ON ELECTRON DEVICES, Journal of Electrical and Electronics Engineering Research (JEEER) and for International Conference - Asia Pacific Microwave Conference (APMC)-2008 held from 16-19, December 2008 in Hong Kong Convention and Exhibition Center, China. Her name has been listed in 2010 edition of Who’s Who in the World. Her name appeared in the GOLDEN REPORT SELECTION.teS T-ED, IEEE TRANSACTIONS ON ELECTRON DEVICES, December 2008.

Research Interest

Modeling and simulation of sub-100 nm MOSFET structures: Insulated Shallow Extension (ISE), Grooved/ Concave Gate, Silicon on Insulator (SOI), Silicon on Nothing (SON), High Electron Mobility Transistor (HEMT).