Binsu J Kailath
Assistant Professor
School of Computer and Electrical Engineering
Indian Institute of Information Technology, Design and Manufacturing
India
Biography
Binsu J Kailath is a Professor Indian Institute of Information Technology, Design and Manufacturing.
Research Interest
Analog and Digital IC Design Device Modeling and Technology MEMS
Publications
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Abdul Majeed K K and Binsu J Kailath (2013): “A Novel Phase Frequency Detector for a High Frequency PLL Designâ€, Procedia Engineering 64, 377 – 384
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E. Papanasam, Binsu J Kailath (2016): â€Effect of Post Deposition Annealing and Post Metallization Annealing on Electrical and Structural Characteristics of Pd/Al2O3/6H-SiC MIS Capacitorsâ€, Accepted for Publication in Microelectronics International Journal
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Abdul Majeed, K.K. Kailath, B.J. (2017) "Low power PLL with reduced reference spur realized with glitch-free linear PFD and current splitting CP", Analog Integrated Circuits and Signal Processing, Online from 21st June 2017, doi:10.1007/s10470-017-1013-4
