Joycee M. Mekie
Assistant Professor
Electrical Engineering
Indian Institute of Technology Gandhinagar
India
Biography
Joycee M. Mekie, PhD (IIT Bombay) is assistant professor. Her research interests include VLSI Design, Asynchronous circuit design.
Research Interest
VLSI Design, Asynchronous circuit design
Publications
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J. Mekie, S. Chakraborty and D. K. Sharma, Jan 2004, "Evaluation of Pausible Clocking Scheme for Interfacing High Speed IP Cores in GALS Framework," in Proc. of International Conference on VLSI Design, pp. 559-564.
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J. Mekie, S. Chakraborty, G. Venkataramani, P. Thiagarajan and D. K. Sharma, March 2006, "Interface Design for Rationally Clocked GALS Systems," in Proc. of ASYNC, pp. 160-171.
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S. Chakraborty, J. Mekie and D. K. Sharma, March 2006, "Reasoning about Synchronization using Abstract Timing Diagrams," in Special Issue on Formal Methods for Globally Asynchronous Locally Synchronous (GALS) Systems, Formal Methods in System Design (FMSD), pp. 153-169, Vol. 28, No. 2.
