Anindya Sundar Dhar
Professor
Electronics and Electrical Communication Engg.
Indian Institute of Technology (IIT) Kharagpur
India
Biography
Ph. D. (Electronics and Electrical Communication Engineering), Dissertation: Cordic based array architectures for electromedical signal processing Indian Institute of Technology, Kharagpur, 1994. M. Tech. (Electronics and Electrical Communucation Engineering), Specialization: Integrated Circuits and Systems Engineering Indian Institute of Technology, Kharagpur, 1989. B. Tech. (Electronics and Telecommunication Engineering), University of Calcutta (Bengal Engineering College), 1987.
Research Interest
VLSI Architecture Design
Publications
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A. S. Dhar and S. Banerjee, “An array architecture for computing discrete Fourier transform to assist semiconductor device modellingâ€, Electronics Letters, vol. 28, No. 7, pp. 697 - 698, 26th March 1992.
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A. S. Dhar and S. Banerjee, “An array architecture for computing two-dimensional discrete Hartley transformâ€, Computers Electrical Engng., vol. 17, No.1, pp. 23 - 29, 1991.
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A. S. Dhar and S. Banerjee, “An array architecture for fast computation of discrete Hartley transformâ€, IEEE Trans. Circuits Systs., vol. 38, No. 9, pp. 1095 - 1098, Sep. 1991.
