Anirban Sengupta

Biography

Dr. Anirban Sengupta is working as Asst. Professor (Associate Professor appointment approved) in the Discipline of Computer Science and Engineering at Indian Institute of Technology (I.I.T) Indore, here he directs the research lab on ‘Behavioural Synthesis of Digital IP core ’. He holds a Ph.D. & M.A.Sc. in Electrical & Computer Engineering from Ryerson University, Toronto (Canada) and is a registered Professional Engineer of Ontario (P.Eng.). He is awarded prestigious IEEE Distinguished Lecturer (Renowned DL of IEEE CE​ ​Society) by IEEE Consumer Electronics Society in 2017. He is recipient of 'Sir Visvesvaraya Faculty Research Fellow' by Ministry of Electronics & IT. He has 117 Publications & Patents & which include Journals, Patents and Invited Book Chapters from IEEE, IET, Elsevier, Springer and USPTO/CIPO/IPO. He is also the recipient of ‘Best Research Paper Award 2017’ by Indian Institute of Technology Indore. He has been awarded highest rating ‘Excellent’ by expert committee of Department of Science & Technology (DST) based on the performance (output) in externally funded project in 2017. His research ideas has been awarded competitive funding of over INR 77 Lakh by various prestigious agencies such as Department of Science & Technology (DST), Council of Scientific and Industrial Research (CSIR) and Department of Electronics & IT (DEITY). He currently serves in Editorial positions as Senior Editor, Associate Editor, Editor and Guest Editor of several IEEE Transactions/Journals, Elsevier, & IET Journals including IEEE Transactions on Aerospace and Electronic Systems (TAES), IEEE Transactions on VLSI Systems, IEEE Access Journal, IET Journal on Computer & Digital Techniques, Elsevier Microelectronics Journal, IEEE Consumer Electronics Magazine, IEEE VLSI Circuits & Systems Letter. He further serves as Guest Editor of IEEE Transactions on Consumer Electronics, IEEE Transactions on VLSI Systems and IEEE Access Journals. He is the Technical Program Chair of 36th IEEE International Conference on Consumer Electronics (ICCE) 2018 in Las Vegas, 15th IEEE International Conference on Information Technology (ICIT) 2016, 3rd IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) 2017 and 2019 IEEE International Symposium on VLSI (ISVLSI) in Florida. Several of his IEEE publications have appeared in 'Top 50 Most Popular Articles' from IEEE Periodicals. He has supervised 4 Ph.D. candidates (2 completed and 2 pursuing) and 6 RA/B.Eng. students, many of whom are/were placed in academia and industry. He holds an external affiliation as 'Honorary Chief Scientist' at VividSparks IT Solutions Pvt Ltd, besides his regular affiliation at IIT-I. His research interest includes Optimization during Design Space Exploration for Hardware Accelerators, High Level Synthesis, Fault Secured High Level Synthesis, Trojan Security Aware HLS, Hardware Trust in High Level Synthesis, IP core Protection during HLS, Evolutionary Computing during HLS as well as Physical Design using CAD. His research/sponsored projects are supported by industries such as Intel Corporation and VividSparks IT Solutions. In the past, his Patents generated funding from Ontario Center of Excellence (OCE), Canada. He had performed industry interactive research extensively for more than 2 years with Calypto, Bluespec, BEECube, Huawei Canada during development of his Ryerson Design Space Exploration Tool arising from his Patent. For his excellence in doctoral research, he has been awarded/nominated by Ministry of Training, Colleges and Universities, Ontario for multiple years through OGS as well as by Ryerson University through GREA, RGA and NSERC ICA for consecutive years.

Research Interest

CAD-VLSI, EDA, High Level Synthesis, IP core Security, Hardware Trojan, Fault Security, Digital Watermark in digital chip, Optimization of Hardware Accelerators, Design Automation.