Dr. Archana Pandey
Assistant Professor
Electronics and Communication Engineering
Jaypee Institute of Information Technology
India
Biography
PhD, Title: “Impact of FinFET Parasitic Effects in Circuit Design”, Indian Institute of Technology, Roorkee M.Tech, Solid state Electronic Materials, Indian Institute of Technology, Roorkee B.Tech, Electronics & Communication Engineering, G. B. Pant Engineering College, Pauri
Research Interest
Novel semiconductor devices, FinFETs, Device modeling, Delay modeling of Digital circuit modules, Digital VLSI circuit design, VLSI device-circuit co-design.
Publications
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A. Pandey, H. Kumar, S. K. Manhas, S. Dasgupta, and B. Anand, “Atypical Voltage transitions in FinFET Multi- Stage Circuits : Origin and Significance,†IEEE Transactions on Electron Devices, vol. 63, no. 3, pp. 1392-1396, March 2016.
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A. Pandey, S. Raycha, S. Maheshwaram, S. K. Manhas, S. Dasgupta, A. K. Saxena, and B. Anand, “Effect of load capacitance and input transition time on FinFET inverter capacitances,†IEEE Transactions on Electron Devices, vol. 61, no. 1, pp. 30-36, 2014.
