Vimal Kumar Mishra
Assistant Professor
Electronics and Communication Engineering
Jaypee Institute of Information Technology
India
Biography
Assistant Professor, ECE Department, JIIT, Noida (July 2017 – Present) Teaching cum Research Fellow, Department of ECE, MMMUT, Gorakhpur (June 2013 – March 2017) Contractual Faculty, Department of ECE, MMMEC, Gorakhpur (July 2012 – June 2013)
Research Interest
Device Modelling and Simulation: MOSFET, PD-SOI MOSFET, FD-SOI MOSFET, FinFET, and Junctionless Transistor Digital Circuit: SRAM Cell, NAND and NOR circuits
Publications
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Vimal Kumar Mishraand R. K. Chauhan, “Area Efficient Layout design of CMOS Device for Digital Circuit Applications†Journal of Nanoengineering and Nanomanufacturing, American Scientific Publishers, vol-6, issue 3, pp. 188-192, 2016.
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Vimal Kumar Mishraand R. K. Chauhan, “Performance Analysis of Modified Source and TDBC based Fully-Depleted SOI MOSFET for Low Power Digital Applications†Journal of Nanoelectronics and Optoelectronics, American Scientific Publishers, vol-12, issue 1, pp. 59-66, 2017 (SCI Journal)
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Vimal Kumar Mishraand R. K. Chauhan, “Area efficient layout design of CMOS circuit for high-density ICs†International Journal of Electronics, Taylor Francis, Published online 21st June 2017 (SCI Journal)
