Dr. Jitendra Kanungo
Assistant Professor
Electronics and Communication Engineering
Jaypee University of Engineering & Technology
India
Biography
Dr. Jitendra Kanungo has completed Ph.D. in the area of Ultra Low Power VLSI Circuit Design from Department of Electronics & Communication Engineering, Indian Institute of Technology (IIT) Roorkee in year 2013. He has received M. Tech. (Micro-electronics) degree from University Centre for Instrumentation & Microelectronics (UCIM), Panjab University Chandigarh in year 2003 and M.Sc. (Electronics) degree from School of Electronics (SOE), Devi Ahilya University Indore in year 2001. During August 2004 to July 2007 he was a lecturer (ECE) in the College of Engineering Roorkee (COER) India. During July 2007 to July 2008 he has worked as Research Fellow in the project entitled “Special Manpower Development Programme in VLSI & related software (SMDP-II)” at the Department of Electronics & Computer Engineering, Indian Institute of Technology Roorkee, India. This project was governed by the Ministry of Communication & Information Technology (MCIT), Govt. of India. He has published thirteen research papers in peer reviewed journals and conferences.
Research Interest
VLSI architecture
Publications
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Jitendra Kanungo and S. Dasgupta, â€Performance Analysis of a Complete Adiabatic System Driven by the Proposed Power Clock Generator.†IOP Science, Journal of Semiconductors, vol. 35, no. 9, pp. 095001-1- 095001-7, Sep. 2014. (SCOPUS)
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Jitendra Kanungo and S. Dasgupta, “Sinusoidal Clocked Sense-Amplifier Based Energy Recovery Flip-Flops,†World Scientific Journal of Circuits, Systems and Computers. vol. 23, no.5, pp. 1450066-1-1450066-19, March 2014. (SCI)
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Jitendra Kanungo and S. Dasgupta, †Analysis of Energy-Efficient Single Phase Adiabatic Logic at Sub-100 nm CMOS Technology,†JUET Research Journal of Science & Technology, vol. 2, no. 1, pp. 133- 138, Jan. 2015.
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D. Nandan, Jitendra Kanungo and A. Mahajan, “An Efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition,†Elsevier, VLSI the integration journal, Vol. 58, pp. 134–141, June 2017. (SCI)
