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Smruti Ranjan Sarangi

Associate Professor
computer science and engineering
The Indian Institutes of Technology, Delhi
India

Biography

He has filed five US patents and has published 66 papers in reputed international conferences and journals. Dr. Sarangi has been awarded the MICRO (International Symposium on Micro-Architecture) best paper award for his work. His work has featured in the MIT Technology Review and on popular technology sites like theregister and slashdot. He has also won the teaching excellence award at IIT Delhi in 2014. He recently published a book(link) on computer architecture titled, ``Computer Organisation and Architecture'', with McGrawHill India in 2014. He currently directs the SRISHTI research group at IIT Delhi, which focuses on core systems and architecture research. The SRISHTI group has recently released the Tejas architectural simulator. Tejas can be used to simulate complex multicore processors. Its unique selling point is that it is written in Java, and is very easy to use and modify. In terms of performance, accuracy, and features it is competitive with other widely used simulators. Other widely used software include the emuArm ARM ISA emulator, and the UsiFe file system. He is perennially in search of smart student colleagues to solve challenging research problems of mutual interest. Please use this site to find relevant information about his research, publications, courses, advice to graduate students and summer interns, views about pursuing higher studies in India and abroad, and relevant contact information.

Research Interest

Computer Architecture, Operating Systems

Publications

  • FP-NUCA: A Fast NOC Layer for Implementing Large NUCA Caches, Anuj Arora, Mayur Harne, Hameedah Sultan, Akriti Bagaria, Smruti R. Sarangi. IEEE Transactions on Parallel and Distributed Systems

  • Lock-free and Wait-free Slot Scheduling Algorithms by Pooja Aggarwal and Smruti R. Sarangi, IEEE Transactions on Parallel and Distributed Systems

  • Area-aware Cache Update Trackers for Post-silicon Validation, Sandeep Chandran, Smruti R. Sarangi, Preeti Panda, IEEE Transactions on VLSI Systems.

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