Dr. Pankaj Kumar Pal (head)
Assistant Professor
Dept. of Electronics Engineering
The National Institute of Technology Uttarakhand
India
Biography
he had completed my Ph.D. research work under the joint-supervision of Dr. S. Dasgupta and Dr. B. K. Kaushik, ECE Dept., IIT Roorkee. My research work has led to many publications in leading peer reviewed international journals/conferences of high impact factor. I have obtained my M.Tech. degree in VLSI Design under E&CE Department, NIT Hamirpur in year 2010.I have about 5 year's research experience during my M.Tech. and Ph.D. work. In these years, my area of research has been broadened from basic circuit design to novel device architectures and its circuit applications. My current research interests include novel MOS based device ciruit co-design, FinFET parasitic extraction, semiconductor device modeling, and low-power advanced memory design
Research Interest
Semiconductor device physics, Microelectronics and VLSI Design
Publications
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Verma, P. K. Pal, S. Mahavar and B. K. Kaushik (2016)"Performance Enhancement of STT MRAM Using Asymmetric-k Sidewall-spacer NMOS," IEEE Trans. on Electron Devices, vol.63. .
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S. Sharma, R. Chandel, P. K. Pal, and R. Rathor ( 2012) "Performance analysis of CNTs as an application for future VLSI interconnects," Jour. of Microelec. and Solid State Electron., SAP, vol.1, no.3, pp.69-73,
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Pal P, B. K. Kaushik, and S. Dasgupta (2017)"High performance variation tolerant circuit/SRAM design using spacer engineered devices," IEEE Trans. on VLSI. (communicated)
