Kiyofumi Tanaka

Biography

â– Degrees B.S., M.S. and Ph.D. from the University of Tokyo (1995, 1997, 2000) â– Professional Career Research Associate(JSPS) at the University of Tokyo (2000), Japan Science and Technology Agency, PRESTO Researcher (2001-2005) â– Specialties Computer Architecture, Parallel Computer, Embedded System

Research Interest

Parallel computer architecture In parallel computer systems, dynamic reduction in messages is an effective scheme for preventing hot-spots which degrade performance. We study how to build a highly functional interconnection network that implements the reduction. Futher, we study adaptive directory scheme for management of shared data. Memory system for large-scale data We propose a reconfigurable cache memory that provides a buffer for large-scale data, and DMA mechanisms by a memory controller where stride data sequences are gathered and transferred efficiently. We evaluate the efficiency of them applied to real applications. Embedded system architecture We develop the RISC core for embedded systems which is configurable about the hardware elements according to demands on speed, size of hardware and consumption of electricity by various applications. Further, we develop real-time operating system which performs adaptive scheduling. In addition, we investigate reduction in electricity consumption for future architecture. Processor Architecture for Real-Time Multitasking A computer is used in multitasking fashion based on time sharing. In this rsearch, we propose the architecture that reduces the time required for switching processor contexts such as register contents and address space when an active task is switched, and alleviates constraints in scheduling of real-time applications.