Tan Chuan Seng

Biography

Chuan Seng Tan received his B.Eng. degree in electrical engineering from University of Malaya, Malaysia, in 1999. Subsequently, he completed his M.Eng. degree in advanced materials from the National University of Singapore under the Singapore-MIT Alliance (SMA) program in 2001. He then joined the Institute of Microelectronics, Singapore, as a research engineer where he worked on process integration of strained-Si/relaxed-SiGe heterostructure devices. In the fall of 2001, he began his doctoral work at the Massachusetts Institute of Technology, Cambridge, USA, and was awarded a Ph.D. degree in electrical engineering in 2006. He was the recipient of the Applied Materials Graduate Fellowship for 2003-2005. In 2003, he spent his summer interning at Intel Corporation, Oregon. He joined NTU in 2006 as a Lee Kuan Yew Postdoctoral Fellow and since July 2008, he was a holder of the inaugural Nanyang Assistant Professorship. In February 2014, he was promoted to the rank of Associate Professor (with tenure). His research interests are semiconductor process technology and device physics. Currently he is working on process technology of three-dimensional integrated circuits (3-D ICs), as well as engineered substrate (Si/Ge/Sn) for photonics. He has numerous publications (journal and conference) and IP on 3-D technology and engineered substrates. He co-edited/co-authored four books on 3D packaging technology. He provides his service as committee member for International Conference on Wafer Bonding, IEEE-3DIC, IEEE-EPTC, IEEE-ECTC, ECS-Wafer Bonding, and ISTDM. He is an associate editor for Elsevier Microelectronics Journal (MEJ). He is a member of IEEE.

Research Interest

3D packaging and integration, Group-IV hetero-epitaxy (Si, Ge, Sn), engineered substrate and devices, Group-IV photonics, III-V/Ge/Si integration.