Dr. Javier Hormigo
Associate Professor
Department of Computer Architecture
Universidad de Malaga
Spain
Biography
Javier Hormigo received his B.S. and M.S. degree in Telecommunication Engineering in 1996 and his Ph.D. in Telecommunication Engineering in 2000, both from the University of Málaga, Spain. He has been working with the Computer Architecture Department of this university as Associate Professor since 2001 . Previously, he was a researcher and assistant professor in the same department (1997-2000) and researcher in the Image and Vision Department of the Instituto de Óptica, Madrid, Spain, in 1996. He has a great experience in the field of computer arithmetic and application specific digital circuits, having more than 15 publications in international Journals and participating in more than 30 international conferences in this area. He is serving as Program Chair for ARITH23 and has served as Programm Committee member for ARITH22. His main research interests are Fixed- and Floating-point arithmetic units, FPGA designs, hardware design for image and signal processing, word-lenght optimization, neural networks and non-conventional arithmetics. He was a Visiting Research Scholar in the Department of Electrical and Computer Engineering of the University of Wisconsin-Madison at Wisconsin (USA) in 2007, and Dept. Electrical Engineering & Computer Science of Lehigh University, Pennsylvania (USA), in 1998 and 1999, for a total of nine months, with Dr. Michael Schulte. He was with ``Lehrstuhl fuer integrierte schaltungen'', Technical University of Munich, (Germany), as visiting research, from March to June, in 2001, working with Prof. Walther Stechele and supported by the DAAD (research grant). Among other subjects, he has mainly taught "Computer Fundamentals", "Computer Architecture", "Specialized Computer Architectures", "Industrial Informatics", "Image Compression", en Higher Technical School of Industrial Engineering and Higher Technical School of Informatic Engineering.
Research Interest
Computer Arithmetic, Application Specific Architectures, FPGA , Signal and Image Processing, Hardware implementations of Neural Networks, Word-length Optimaization
Publications
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Hormigo J, Villalba J. New formats for computing with real-numbers under round-to-nearest. IEEE Transactions on Computers. 2016 Jul 1;65(7):2158-68.
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Senthilvelan M, Hormigo J, Chun JH, Sima M, Iancu D, Schulte M, Glossner J. CORDIC-based LMMSE equalizer for Software Defined Radio. InEmbedded Computer Systems (SAMOS), 2010 International Conference on 2010 Jul 19 (pp. 301-308). IEEE.
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Hormigo J, Villalba J. Simplified floating-point units for high dynamic range image and video systems. InConsumer Electronics (ISCE), 2015 IEEE International Symposium on 2015 Jun 24 (pp. 1-2). IEEE.
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Muñoz SD, Hormigo J. Improving fixed-point implementation of QR decomposition by rounding-to-nearest. InConsumer Electronics (ISCE), 2015 IEEE International Symposium on 2015 Jun 24 (pp. 1-2). IEEE.
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Hormigo J, Villalba J. Optimizing DSP circuits by a new family of arithmetic operators. InSignals, Systems and Computers, 2014 48th Asilomar Conference on 2014 Nov 2 (pp. 871-875). IEEE.
