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Henry Chen

Professor
Department of Electrical Engineering
Wright State University
United States of America

Biography

Professor Henry Chen received his Ph.D. degree from the University of Minnesota, Minneapolis, in 1989, in electrical engineering. Since joining Wright State University in 1989 he has worked primarily in the area of digital and mixed-signal integrated circuits, VLSI/FPGA/GPU for signal processing and ultra wideband receivers, and smart printed electronics for sensors, where he is currently a Professor. Professor Chen collaborates with researchers from a range of disciplines to advance the development of ultra wideband receivers for efficiently collecting, analyzing and classifying signals in noisy signal environment within a wide radio-frequency spectrum. Academics Teaching: COURSE TAUGHT RECENTLY EE7510 - Digital Wideband Receiver Design EE7520 - Low Power VLSI System Design EE7540 - VLSI Testing and Design for Testability EE4540 - VLSI Design EE3310 - Electronic Devices and Circuits EE2000 - Digital Design with VHDL EE8000 - Mixed Signal Tools Research statement:

Research Interest

Digital and mixed-signal integrated circuits, VLSI/FPGA/GPU for signal processing and ultra wideband receivers, smart printed electronics for sensors. Domains - Electronic warfare, cyber security, VLSI, FPGA, GPU, smart printed electronics.

Publications

  • Benson, S. and Chen, C.-I. H., Lin, M. D. and Liou, L. L., “High Linear Chirp Receiver Using High Resolution Time-of-Arrival Estimation,” IEEE Transactions on Aerospace and Electronic Systems, 2016. Vol. 52, No. 3. pp. 1146-1154, June 2016.

  • Lin, E., Chen, C.-I. H., Liou, L. L. and Lin, D. M., “Performance Analysis of Digital Wideband Receiver based on Reconstruction of Compressive Sensing Data,” accepted for presentation in 2017 IEEE Radar Conference, Seattle, WA, May 2017.

  • Wang, Y., Chen, J. and Chen, C.-I. H., “Chebyshev Bandpass Filter Using Resonator of Tunable Active Capacitor and Inductor, VLSI Design, Vol. 2017, Article ID 5369167, 12 pages, 2017.

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