Jiafeng Xie
Ph.D.
Department of Electrical Engineering
Wright State University
United States of America
Biography
Dr. Xie is an Assistant Professor in the Department of Electrical Engineering at the Wright State University, Fairborn, OH. He received his Ph.D. degree in electrical engineering from University of Pittsburgh, Pittsburgh, in 2014. He joined the Wright State University as an Assistant Professor in 2015. He is currently serving on the editorial board of Microelectronics Journal (Elsevier). Students interested in join my research group are encouraged to contact me and attach their CVs. Education History: Ph.D. University of Pittsburgh, 2014. Academics Teaching: Spring 2015: EE 2010 Circuits Analysis Fall 2015: EE 4800/6800 Algorithms to VLSI Architectures Spring 2016: EE 8000 VLSI Cryptographic Circuits Spring 2016: EE 2010 Circuits Analysis Fall 2016: EE 2000 Digital Design Fall 2016: EE 4800/6800 Algorithms to VLSI Architectures Spring 2017: EE 8000 VLSI Cryptographic Circuits Spring 2017: EE 2010 Circuits Analysis
Research Interest
Hardware security, VLSI cryptographic circuits, systolic structure design and its application in cryptosystem, intelligent system security and fault detection, and VLSI digital processing systems design
Publications
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J. Xie, P.K. Meher, M. Sun, Y. Li, B. Zeng, and Z.-H. Mao. Efficient FPGA implementation of low-complexity systolic Karassuba multiplier over GF(2m) based on NIST polynomials. IEEE Trans. Circuits & Systems-I: Regular Papers, vol. 64, no. 7, pp. 1815-1825, 2017.
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M. M-Kermani, A. Jalali, R. Azarderakhsh, J. Xie, and K.K. R. Choo. Reliable inversion in GF(28) with redundant arithmetic for secure error detection of cryptographic architectures. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, accepted, 2017.
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Q. Shao, Z. Hu, S. Chen, P. Chen, and J. Xie. Low-complexity digit-level systolic Gaussian normal basis multiplier. IEEE Trans. VLSI Systems, accepted, 2017.
